ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Assumptions of Use for FuSa purposes
We expect that:
•
The GIC-600AE connects directly to the far-end IP with only wires and repeater buffers
•
No complex logic gates such as ADBs or crossbar switches exist in the path, because they could
be a source of Multiple-Bit Errors (MBEs)
•
The far-end IP checks the parity bits that the GIC-600AE generates
•
The far-end IP generates the incoming parity bits, as the following table describes
Table 6-7: ACE-Lite interface parity
Check signal Signals covered Width Granularity Check enable
awvalidchk awvalid 1 1 -
awreadychk awready 1 1 -
awidchk awid ceil(IdWidthW/8) IdWidthW awvalid==1
awaddrchk awaddr ceil(AddrWidth/8) 1-8 awvalid==1
awlenchk awlen 1 8 awvalid==1
awctlchk0 awsize, awburst, awlock, awprot 1 1-9 awvalid==1
awctlchk1 awregion, awcache, awqos 1 4-12 awvalid==1
awctlchk2 awdomain, awsnoop, awunique, awbar 1 4-9 awvalid==1
awuserchk awuser ceil(AWUserWidth/8) 1-8 awvalid==1
awatopchk
12
awatop 1 6 awvalid==1
wvalidchk wvalid 1 1 aresetn==1
wreadychk wready 1 1 aresetn==1
wdatachk wdata DataWidthW/8 8 wvalid==1
wstrbchk wstrb ceil(DataWidthW/64) 1-8 wvalid==1
wlastchk wlast 1 1 wvalid==1
wuserchk wuser ceil(WUserWidth/8) 1-8 wvalid==1
bvalidchk bvalid 1 1 aresetn==1
breadychk bready 1 1 aresetn==1
bidchk bid ceil(IdWidthW/8) IdWidthW bvalid==1
brespchk bresp 1 2 bvalid==1
buserchk buser ceil(BUserWidth/8) 1-8 bvalid==1
arvalidchk arvalid 1 1 aresetn==1
arreadychk arready 1 1 aresetn==1
aridchk arid ceil(IdWidthR/8) IdWidthR arvalid==1
araddrchk araddr ceil(AddrWidth/8) 8 arvalid==1
arlenchk arlen 1 8 arvalid==1
arctlchk0 arsize, arburst, arlock, arprot 1 1-9 arvalid==1
arctlchk1 arregion, arcache, arqos 1 4-12 arvalid==1
arctlchk2 ardomain, arsnoop, arbar 1 4-8 arvalid==1
12
awatop is used for atomics, and is only visible when atomic_support==1
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