Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.2.1 GICD_CTLR, Distributor Control Register
This register enables interrupts and affinity routing.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
The EnableGrp* bits and the RWP bit must be 0 before the DS bit can be updated. A write that
sets the DS bit must also set the EnableGrp* bits to 0.
Bit descriptions
Figure 5-1: GICD_CTLR bit assignments
31 8 7 6 5 4 3 2 1
0
EnableGrp1S
Reserved
ARE_S
ARE_NS
DS
E1NWF
30
RWP
Reserved
EnableGrp0
EnableGrp1NS
Table 5-3: GICD_CTLR bit descriptions
Bits Name Description Type Reset
[31] RWP Register Write Pending:
0 No register write in progress
1 Register write in progress
RO 0
[30:8] - Reserved - -
[7] E1NWF Enable 1 of N Wakeup Functionality RW 0
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