ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-25: GICR_PIDR2 bit assignments
ArchRevReserved
31 8 7 4 3
DES_1
02
JEDEC
Table 5-29: GICR_PIDR2 bit descriptions
Bits Name Description
[31:8] - Reserved, RAZ
[7:4] ArchRev Identifies the version of the GIC architecture with which the Redistributor complies:
0x3 GICv3
[3] JEDEC Indicates that a JEDEC-assigned JEP106 identity code is used
[2:0] DES_1 Bits[6:4] of the JEP106 identity code. Bits[3:0] of the JEP106 identity code are assigned to
GICR_PIDR1[7:4].
5.5 Redistributor registers for SGIs and PPIs summary
The functions for the GIC-600AE SGIs and PPIs are controlled through the Redistributor registers
identified with the prefix GICR.
For descriptions of registers that are not specific to the GIC-600AE, see the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
Table 5-30: Redistributor registers for SGIs and PPIs summary
Offset Name Type Reset Width Description Architecture
defined?
0x0000-
0x007C
- - - - Reserved -
0x0080 GICR_IGROUPR0 RW 0x0 32 Interrupt Group Register Yes
0x0084-
0x0FFC
- - - - Reserved -
0x0100 GICR_ISENABLER0 RW 0x0 32 Interrupt Set-Enable Register Yes
0x0104-
0x017C
- - - - Reserved -
0x0180 GICR_ICENABLER0 RW 0x0 32 Interrupt Clear-Enable Register Yes
0x0184-
0x01FC
- - - - Reserved -
0x0200 GICR_ISPENDR0 RW PPI wire dependent 32 Interrupt Set-Pending Register Yes
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