ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Record GICT_ERR<n>STATUS.IERR (syndrome) GICT_ERR<n>STATUS
.SERR
Value and description of
GICT_ERR<n>MISC0.Data (other bits
RES0)
Always packed from 0 (lowest = 0)
Uncorrectable
PPI RAM
errors (8)
0x00 0x7
Correctable
LPI RAM
errors (9)
0x00 0x7
Uncorrectable
LPI RAM
errors (10)
0x00 0x7
See Table 4-12: LPI RAM errors,
records 9-10 on page 80
Correctable
error from ITS
RAM (11)
0x00 0x6
Uncorrectable
error from ITS
RAM (12)
0x00 0x6
See Table 4-13: ITS RAM errors,
records 11-12 on page 80
Command or
translation
error in ITS
(13+)
0x00 architectural
0x01 non-architectural
0x1 ITS 24-bit syndrome. See 4.15.6.7 ITS
command and translation error records
13 and beyond on page 81.
5.8.6 GICT_ERR<n>MISC1, Error Record Miscellaneous Register 1
This register contains the data value of an uncorrectable error in the LPI RAM or ITS software
information for one of 13, or more, error records. The GIC-600AE only supports a single MISC1
register, so n = 10, and therefore this register is identified as GICT_ERR10MISC1.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
If GICT_ERR10STATUS.MV == 1, then GICT_ERR10MISC1 ignores writes.
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