ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The GICT_ERR<n>MISC0 register reports data for LPI error records 9-10 shown in the following
table.
Table 4-12: LPI RAM errors, records 9-10
Record GICT_ERR<n>MISC0.Data
9 = Correctable •
Bit location, bits[14+]
•
Pending, bits[13:12]. These bits indicate if there were pending interrupts in the cache at the
time of the corruption.
•
Reserved, bits[11:10].
•
Address, bits[9:0]
10 =
Uncorrectable
•
Pending, bits[13:12]
•
Reserved, bits[11:10]
•
Address, bits[9:0]
When an uncorrectable error occurs, the data shown in the table is stored and the
GICT_ERR<n>MISC1 register is updated to contain the RAM contents of the corrupted line. The
line in RAM is dropped, and any pending interrupts that it might contain are lost.
If required, software can use the data in the GICT_ERR<n>MISC1 register to check several
interrupt sources, such as the corrupted INTID. This ID is never more than two bits away from the
recorded ID.
4.15.6.6 ITS RAM error records 11-12
ITS RAM error record 11 records ITS RAM ECC errors that are correctable. ITS RAM error record
12 records ITS RAM ECC errors that are uncorrectable.
ITS RAM error records 11-12 are present if an ITS is configured.
Error records 11-12 record the errors from ITS RAM.
All ITS tables are memory backed allowing uncorrectable errors to be read from RAM again without
software intervention. These records are used for tracking RAM errors and for possible RAM
maintenance.
The GICT_ERR<n>MISC0 register reports data for ITS RAM error records 11-12 shown in the
following table.
Table 4-13: ITS RAM errors, records 11-12
Record GICT_ERR<n>MISC0.Data
11 = Correctable •
Address, bits[31:x + 10]
•
Bit location, bits[x + 9:x + 2]
•
RAM, bits[x + 1:x]
•
ITS, bits[x − 1:0]
Where x = log
2
(ITS)
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 80 of 268