Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
8.
Re-enable the reprogrammed interrupts by writing to the relevant GICR_ISENABLER0.
9.
Recheck the error record, to ensure that no more errors are reported. If necessary, repeat the
recovery sequence from step 2 on page 78.
4.15.6.4 PPI RAM error records 7-8
PPI RAM error record 7 records RAM ECC errors that are correctable. PPI RAM error record 8
records RAM ECC errors that are uncorrectable.
Error records 7-8 record the errors from PPI RAM that contain GICR_IPRIORITYRn information
for PPIs and SGIs. PPI RAM also contains a buffer that stores generated SGIs when backpressure
occurs.
The GICT_ERR<n>MISC0 reports data for PPI error records 7-8 shown in the following table.
Table 4-11: PPI RAM errors, records 7-8
Record GICT_ERR<n>MISC0.Data
7 = Correctable •
PPI block, bits[18+]
•
Bit location, bits[17:12]
•
Offset, bits[11:8]
•
SGI/Int, bit[7]
•
Core, bits[6:0]
8 = Uncorrectable •
PPI block, bits[12+]
•
Offset, bits[11:8]
•
SGI/Int, bit[7]
•
Core, bits[6:0]
For uncorrectable errors, if:
Bit[7], SGI/Int == 0
Software must perform the recovery sequence that 4.15.6.3 SGI RAM error records 3-4 on
page 77 describes.
Bit[7], SGI/Int == 1
The GIC did not generate the SGI because an error occurred during SGI generation. Although
an SGI generation error occurs, the GIC continues to operate normally.
4.15.6.5 LPI RAM error records 9-10
LPI RAM error record 9 records RAM ECC errors that are correctable. LPI RAM error record 10
records RAM ECC errors that are uncorrectable. Each error generates an LPI interrupt.
LPI RAM error records 9-10 are present if LPI support is configured.
The LPI RAM is the main LPI cache and it stores the LPI properties and pending information.
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