Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The Distributor records a subset of the SGI programming, and stores this information in the SGI
RAM, to ensure that it can make the correct routing decisions for SGIs.
If a correctable error is detected in SGI RAM, the error is corrected and the error is reported
in error record 3. See 4.15.5 Error recovery and fault handling interrupts on page 70 for
information about the error counters and interrupt generation options.
Correctable errors do not require software to take any action within the GIC. However, the GIC
can choose to track error locations in case a RAM row or column can be repaired, and the RAM has
repair capability.
The GICT_ERR<n>MISC0 reports data for SGI error records 3-4 shown in the following table.
Table 4-10: SGI RAM errors, records 3-4
Record GICT_ERR<n>MISC0.Data
3 = Correctable •
Bit location, log
2
(width)
•
Address, bits[(ceil(cores / 16) × 16) − 1:0]
4 = Uncorrectable Address, bits[(ceil(cores / 16) × 16) − 1:0]
The RAM stores information for the same SGI for up to 16 cores on a single row. The corrupted
SGI number is given by:
•
address MOD 16 on cores (address − (address MOD 16)) to (address − (address MOD 16)) + 15
GICR_SGIDR contains default values for GICR_IGROUPR0, GICR_IGRPMODR0, and GICR_NSACR
for each SGI.
When an SGI is in error, the GIC operates using the values that GICR_SGIDR contains.
For uncorrectable errors that occur in either the PPI or SGI RAM, software is required to perform
the following recovery sequence:
1.
Read the error record, to determine if an uncorrectable error has occurred.
2.
Clear the error record, to enable future errors to be tracked.
3.
Read all GICR_IERRVR registers, so that you can identify the SGIs or PPIs that have errors. The
GICR_IERRVR registers must be read from the Secure side.
4.
If necessary, read out any of the current programmed states. This includes programmed
data that is corrupted and generates an error, unless GICT_ERR0CTRL.UE is disabled. We
recommend that intended programming is stored in memory so that this step is not required.
The GICR_NSACR is overwritten when an error occurs, so the pre-error value cannot be read
back at this stage.
5.
Write to GICR_ICENABLER0, to disable all interrupts that have errors.
6.
Write 1 to the GICR_IERRVR bits that step 3 indicates are showing an SGI or PPI error.
This write clears the interrupt error and reverts the corresponding GICR_IGROUPR0,
GICR_IGRPMODR0, and GICR_NSACR bits to their default values. The values of PPIs are not
changed.
7.
Reprogram the interrupt to the intended settings.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 78 of 268
To Next Page
Loading...