Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
The software must be aware of the power state of the remote blocks and not initiate writes to
these registers that target a powered-down remote GIC block. If software initiates a write to the
following registers that target a powered-off remote GIC block, then:
•
FMU_ERR<n>STATUS ignores the write for all purposes. FMU_ERR<n>STATUS is unchanged.
•
FMU_PINGNOW ignores the write for all purposes other than reading back the register. It does
not send a PING packet and does not indicate that the FMU is non-idle through FMU_STATUS.
•
FMU_SMEN ignores the write for all purposes
•
FMU_SMINJERR ignores the write for all purposes
6.3 FuSa programmer's view
The FMU contains the functional safety registers.
The GIC-600 memory map that is used to address the legacy GIC functional logic is unchanged on
GIC-600AE. See 5. Programmers model on page 95 for the functional GIC-600 memory map.
GIC-600AE uses a separate and independent memory map for the Fault Detection and Control
(FDC) programmer's view. For a description of the registers that are specific to GIC-600AE, see
5.10 FMU register summary on page 179.
6.4 FuSa I/O
Ports have been added for FuSa fault detection and control.
See 6.8 External interface protection on page 221 for more information about the new
interfaces.
6.4.1 Non-architected FuSa ports
The following ports have been added for fault detection and control.
In the following table, Granularity refers to the hierarchy or the block in which the ports are
relevant.
Table 6-3: Non-architected FuSa ports
Port Direction Granularity Description
clk_fdc Input Per domain Clock for redundant logic and SMs
reset_n_fdc Input Per domain Reset for redundant logic and SMs
nmbistreset_fdc Input Per domain Redundant nmbistreset signal. Both resets must assert together.
dbg_reset_n_fdc Input GICD
domain
Redundant dgb_reset_n reset signal for PMU and FMU. Both resets must assert
together.
dftrstdisable_fdc Input All domains Prevents reset from asserting when reset generation FDC flops are scanned
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