Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-4: GICD_TYPER bit assignments
Bits Name Description
[31:26] - Reserved, returns 0b000000
[25] No1N 1 of N SPI:
0 The GIC-600AE supports 1 of N SPI interrupts.
[24] A3V Affinity level 3 values. Depending on the configuration, returns either:
0 The GIC-600AE Distributor only supports zero values of affinity level 3.
1 The GIC-600AE Distributor supports nonzero values of affinity level 3.
[23:19] IDbits Interrupt identifier bits:
0b01111 The GIC-600AE supports 16 interrupt identifier bits.
[18] DVIS Direct virtual LPI injection support:
0 The GIC-600AE does not support direct virtual LPI injection.
See the GICv3 and GICv4 Software Overview.
[17] LPIS Indicates whether the implementation supports LPIs. Depending on the configuration, returns either:
0 LPIs are not supported
1 LPIs are supported
[16] MBIS Message-based interrupt support:
1 The GIC-600AE supports message-based interrupts.
[15:11] num_LPIs Returns 0b00000 because GICD_TYPER.IDbits indicates the number of LPIs that the GIC supports.
[10] SecurityExtn Security state support. Depending on the configuration, returns either:
0 The GIC-600AE supports only a single Security state.
1 The GIC-600AE supports two Security states.
When GICD_CTLR.DS == 1, this field is RAZ.
[9:8] - Reserved, returns 0b00000
[7:5] CPUNumber Returns 0b000 because GICD_CTLR.ARE==1 (ARE_NS & ARE_S).
[4:0] ITLinesNumber Returns the maximum SPI INTID that this GIC-600AE implementation supports, and is given by
32×(ITLinesNumber + 1) − 1.
5.2.3 GICD_IIDR, Distributor Implementer Identification Register
This register provides information about the implementer and revision of the Distributor.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
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