Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
To reduce memory traffic and keep interrupt latency to a minimum, GIC-600AE has three two-way
set associative caches in each ITS:
•
DeviceID to ITT base address.
•
DeviceID and EventID to collection.
•
Collection to target core.
In small configurations, these caches might be too small to be worth the overhead of implementing
them as SRAM. If ECC protection is not required for a cache that is implemented as an array of
flops, and to reduce RAM area, you can remove ECC from each RAM individually. See the Arm
®
CoreLink
™
GIC-600AE Generic Interrupt Controller Configuration and Integration Manual for more
information.
It is common for the DeviceID to be a non-contiguous number that is derived from the PCIe
RequestorID. To ensure that this does not result in a sparse DeviceID table and wasted memory,
the GIC-600AE supports indirect Device tables (GITS_BASERn.Indirect = 1) where the first-
level table points at subtables that can be allocated at runtime. See the Arm
®
Generic Interrupt
Controller Architecture Specification, GIC architecture version 3 and version 4 for more
information.
The GIC-600AE uses memory-backed collections only, which means that before the ITS is
enabled by writing to GITS_CTLR.Enabled, memory must be allocated for the Device table, the
Collection table, and the ITS Command queue. Inline with the architecture, software must pre-clear
these tables to 0, apart from pointers to cleared level-two Device tables, unless the tables were
previously populated by GIC-600AE.
The GIC-600AE ITS supports all GICv3 commands that the Arm
®
Generic Interrupt Controller
Architecture Specification, GIC architecture version 3 and version 4 describes.
GITS_TYPER.PTA is 0 for all configurations, which means that all references to processor cores in
ITS commands are implemented through the GICR_TYPER.ProcessorNumber field.
Command and translation errors are reported through the RAS registers. See 4.15 Reliability,
Accessibility, and Serviceability on page 68.
For information about how to program and use the ITS, see the GICv3 and GICv4 Software
Overview.
4.9.1 ITS cache control, locking, and test
The GIC-600AE can lock certain interrupt translations in the EventID cache.
If a translation is missed in a cache, several memory reads can be required to obtain the data
necessary from memory. This behavior can result in a range of latency that might not be acceptable
for some LPIs.
The GIC-600AE can lock certain translations into the ITS cache, with the following guarantee:
•
Interrupts that are locked in ITS caches, always hit and never require any translation.
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