Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-66: GICP_INTENCLR0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
[4:0] INTEN Interrupt enable. The INTEN[n] bit is the interrupt disable for counter n. This field resets to an unknown
value. Reads return the state of the interrupt enables.
Writing:
Bit[n] = 1 Clears the interrupt enable for counter n
Bit[n] = 0 No effect. To set a counter interrupt enable, use GICP_INTENSET0.
5.9.9 GICP_OVSCLR0, Overflow Status Clear Register 0
This register provides the clear mechanism for the counter overflow status bits and provides read
access to the counter overflow status bit values. The GIC-600AE supports five counters, n = 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-54: GICP_OVSCLR0 bit assignments
31 5 4
0
OVSReserved
Table 5-67: GICP_OVSCLR0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
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