Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
•
The AMBA
®
AXI4-Stream protocol. See the AMBA
®
4 AXI4-Stream Protocol Specification.
•
The GIC Stream protocol. See the GIC Stream Protocol interface appendix in the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
2.3 Features
The GIC-600AE provides interrupt services and masking, registers and programming, interrupt
grouping, security, performance monitoring, and error correction.
Interrupt services and masking
The GIC-600AE provides the following interrupt services and masking features:
•
Support for the following interrupt types:
◦ Up to 56000 LPIs. A peripheral generates these interrupts by writing to a memory-mapped
register in the GIC-600AE. See 3.1.6 Distributor configuration on page 30.
◦ Up to 960 SPIs in groups of 32. See 3.1.6 Distributor configuration on page 30.
◦ Up to 16 PPIs that are independent for each core and can be programmed to support either
edge-triggered or level-sensitive interrupts. See 3.2.5 Redistributor configuration on page
33.
◦ Up to 16 SGIs that are generated through the GIC CPU interface of a core.
•
Up to eight ITS modules that provide device isolation and ID translation for message-based
interrupts and enable virtual machines to program devices directly.
•
Interrupt masking and prioritization with 32 priority levels, five bits per interrupt.
Registers and programming
The GIC-600AE provides the following programming features:
•
Flexible affinity routing, using the Multiprocessor Identification Register (MPIDR) addresses,
including support for all four affinity levels.
•
Single ACE-Lite subordinate port on each chip for programming of all GIC Distributor (GICD)
registers, GIC Interrupt Translation Service (GITS) registers, and GIC Redistributor (GICR) registers.
Each ITS has an optional ACE-Lite subordinate port for programming the GITS_TRANSLATER
register.
•
Coherent view of SPI register data across multiple chips.
Security
The GIC-600AE provides the following security features:
•
A global Disable Security (DS) bit. This bit enables support for systems without security.
•
The following interrupt groups allow interrupts to target different Exception levels:
◦ Group 0
◦ Non-secure Group 1
◦ Secure Group 1
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