Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The core powerdown sequence that you use must match the core powerdown
sequence that is described in the Technical Reference Manual for your
processor.
When a core is powered down and the GICR_WAKER.ProcessorSleep bit is set to 1, if the
GIC-600AE receives an interrupt that targets only that core, the Wake Request block asserts the
wake_request signal that corresponds to that core. The wake_request signal must connect to the
system power controller. See 3.6 Wake Request on page 44.
You must not set the GICR_WAKER.ProcessorSleep bit to 1, unless the core enters a power state
where the GIC-600AE uses the power controller to wake the core instead of the GIC Stream
interface. For example, with Arm
®
Cortex
®
-A53 and Cortex
®
-A57 processors, if a core enters a
low-power state that is based on the Wait For Interrupt (WFI) or Wait For Event (WFE) instructions,
such as retention, you must not set the GICR_WAKER.ProcessorSleep bit to 1.
Interrupts can cause the core to leave the low-power state, entered by executing a WFI or
WFE instruction, as defined in the Arm
®
Architecture Reference Manual Armv8, for A-profile
architecture. The system integrator can use a cpu_active signal to ensure that interrupts that can
target multiple cores are much less likely to target cores in certain low-power states. In such a
system, software has more control of the conditions under which cores leave low-power states.
Interrupts that target only one core are unaffected by the cpu_active signal and are always sent to
that core. Moreover, if the GICR_WAKER.ProcessorSleep bit for that core is set, the wake_request
signal is asserted for that core.
See the Arm
®
Generic Interrupt Controller Architecture Specification, GIC architecture version
3 and version 4 for information about power management, and about wakeup signals and their
relation to the core outputs.
4.6.3 Other power management
The GIC-600AE can be powered up and powered down using non-architectural protocols.
When powering down the GIC-600AE, software must preserve the state of the GIC-600AE, except
for any LPI pending interrupts that are preserved in pending tables, as defined in the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
You can preserve the LPI pending bits by using an implementation-defined powerdown sequence,
which ensures that the memory pointed to by each GICR_PENDBASER contains the updated
pending information for the LPIs. The implementation-defined powerdown sequence must:
1.
Complete the powerdown sequence for all cores.
2.
Set GICR_WAKER.Sleep to 1.
3.
Poll GICR_WAKER until GICR_WAKER.Quiescent is set.
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