Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
• GICR_WAKER.Sleep can only be set to 1 when:
◦ All Redistributors have GICR_WAKER.ProcessorSleep == 1.
◦ All Redistributors have GICR_WAKER.ChildrenAsleep == 1.
• GICR_WAKER.ProcessorSleep can only be set to 0 when:
◦ GICR_WAKER.Sleep == 0.
◦ GICR_WAKER.Quiescent == 0.
• If software decides to abort a sleep request due to an external wake request,
it can do so by clearing GICR_WAKER.Sleep at any time. Software does not
have to wait for GICR_WAKER.Quiescent to be set.
• There is only one GICR_WAKER.Sleep and one GICR_WAKER.Quiescent
bit that can be read and written through the GICR_WAKER register of any
Redistributor.
The powerdown described sequence ensures that all LPIs that are acknowledged by a write
response to the write GITS_TRANSLATER are saved to the Pending tables. Any interrupt that
arrives when the Sleep bit is set to 1 is ignored, and the ACE-Lite transaction completes in
accordance with the ACE protocol.
We recommend that you disable any interrupt sources before setting GICR_WAKER.Sleep.
However, if you require wake-on-interrupt behavior, the write to GITS_TRANSLATER must be
gated upstream at a location that enables software to reprogram and enable the GIC-600AE
without deadlock.
When the GICR_WAKER.Quiescent bit is set, it is safe to power down the GIC-600AE without
losing LPI pending bits. Software must still perform other steps such as the save and restore of SPI
state. However, you must provide custom mechanisms to wake the GIC-600AE if any interrupts
arrive that must not be ignored.
When the GIC-600AE next powers up, you can program the GICR_PENDBASER registers to point
to the same memory to reload the LPI pending status. If there is no requirement to reload the
pending LPIs, we recommend that you speed up the initialization of the GIC-600AE as follows:
1.
Zero the Pending table.
2.
Set GICR_PENDBASER.PTZ to 1.
GICR_PENDBASER registers can only be modified before the
GICR_CTLR.Enable_LPIs bit is set, or when the GICR_WAKER.Sleep and
GICR_WAKER.Quiescent bits are both set.
For more information, see the GICv3 and GICv4 Software Overview.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
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