ARM CoreLink GIC-600AE - 4.3 Physical Interrupt Signals

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
0 Security enabled (fixed)
1 Security disabled (fixed)
P Security is programmable by software during the boot sequence using
GICD_CTLR.DS.
Setting the Disable Security (DS) bit to 1 in the GICD_CTLR register removes the security support
of the GIC-600AE. It can be set by Secure software during the boot sequence or configured to be
always set when you configure the design using the ds_value parameter. When the system has no
concept of security, you must set GICD_CTLR.DS to allow access to important registers.
If you set GICD_CTLR.DS to 1, only a single Security state is supported. In a single Security state,
register access, and the behavior and number of interrupt groups supported are affected. For more
information, see Interrupt grouping, and Interrupt grouping and security in the Arm
®
Generic Interrupt
Controller Architecture Specification, GIC architecture version 3 and version 4.
We recommend that you only set GICD_CTLR.DS if either your system does not
support security, or the only software you run does not use security. See Security
model in the GICv3 and GICv4 Software Overview for more information about the
implications of setting GICD_CTLR.DS to 1.
If you run software without security awareness on a system that supports security, the Secure
boot code can set DS before switching to a Non-secure Exception level to run the software. This
enables you to program the GIC-600AE from any Exception level and use two interrupt groups,
Group 0 and Group 1, so that interrupts can target both the FIQ and IRQ handlers on a core.
Group 0 is always Secure in systems with security. If you decide to write security-unaware software
using Group 0, it might not be portable to systems with a concept of security. Security-unaware
software is most portable when written using Group 1.
If a system has a concept of security but one or more cores do not, then you must not set DS.
Instead each core is only able to enable the interrupt groups corresponding to the Security states
that it supports.
In security aware systems, Secure software can prevent the DS bit from being written by writing to
Disable Security Lock bit, GICD_SAC.DSL. When set, only a hardware reset can clear the DSL bit.
If you know that your system is always security aware, then we recommend configuring the
GIC-600AE without DS support.
For more information, see the Arm
®
Generic Interrupt Controller Architecture Specification, GIC
architecture version 3 and version 4 and the GICv3 and GICv4 Software Overview.
4.3 Physical interrupt signals (PPIs and SPIs)
The GIC-600AE supports two types of physical interrupt signal.
The two types of physical interrupt signal are:
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 52 of 268