Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
If the programmed ID value is less than 32, out of range, or not owned on chip for multichip
configurations, the register updates to 0 and no internal delivery occurs.
We recommend that if the err_int and fault_int signals are internally routed, the target interrupts
must not have SPI Collator wires, or if they are present they are tied off. This recommendation
prevents software checking for the same ID at multiple destinations.
The err_int and fault_int signals do not have direct test enable registers. You can test connectivity
using error record 0 and triggering an error, such as an illegal AXI access to a nonexistent register.
4.15.6 Error handling records
The GIC-600AE has several error records. The range of error handling records that are available
depends on the configuration of the GIC-600AE.
The following table lists the GIC-600AE error handling records. The Type column uses the
following acronyms:
CE Correctable error
UEO Restartable error and contained
UER Recoverable error
Table 4-7: Error handling records
Record Description Type Description, events, and recovery sequences
0 Software error in GICD programming UEO Table 4-8: Software errors, record 0 on page 72
1 Correctable SPI RAM errors CE
2 Uncorrectable SPI RAM errors UER
Table 4-9: SPI RAM errors, records 1-2 on page 76.
GICT_ERR<n>STATUS.SERR == 7, data value from associative memory.
3 Correctable SGI RAM errors CE
4 Uncorrectable SGI RAM errors UER
Table 4-10: SGI RAM errors, records 3-4 on page 78.
GICT_ERR<n>STATUS.SERR == 7, control value from associative memory.
5 Reserved - -
6 Reserved - -
7 Correctable PPI RAM errors CE
8 Uncorrectable PPI RAM errors UER
Table 4-11: PPI RAM errors, records 7-8 on page 79.
GICT_ERR<n>STATUS.SERR == 7, control value from associative memory.
9 Correctable LPI RAM errors CE
10 Uncorrectable LPI RAM errors UER
Table 4-12: LPI RAM errors, records 9-10 on page 80.
GICT_ERR<n>STATUS.SERR == 7, control value from associative memory.
Records 9-10 are not present if there is no LPI support.
11 Correctable error from ITS RAM CE
12 Uncorrectable error from ITS RAM UEO
Table 4-13: ITS RAM errors, records 11-12 on page 80.
GICT_ERR<n>STATUS.SERR == 6, data value from associative memory.
Records 11-12 are not present if an ITS is not present.
13+ ITS command and translation errors UER 4.15.6.7 ITS command and translation error records 13 and beyond on page 81.
GICT_ERR<n>STATUS.SERR == 14, illegal access.
One record per ITS on the chip. Records 13+ are not present if an ITS is not present.
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