ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
GICT_ERR<n>STATUS.IERR
(Syndrome)
GICT_ERR<n>STATUS
.SERR
GICT_ERR<n>MISC0.
Data description
(other bits RES0)
Always packed from
0 (lowest = 0)
Recovery, prevention
0x45, SYN_PT_TABLE_WRITE_FAIL
An attempt was made to write-back
a block of interrupts from a Pending
table, with an error received with the
write response.
0x12 Target, bits[29:16]
ID, bits[15:0]
The GIC tries to continue, however, this error
indicates issues with the memory system, and
operation might be unpredictable
0x46,
SYN_PT_SUB_TABLE_READ_FAIL
An attempt was made to read a
subblock of interrupts from a Pending
table, where an error response was
received with the data.
0x12 Target, bits[29:16]
ID, bits[15:0]
Software must determine the reason for the
pending error read fail. The GIC uses the data
that is supplied, however, it is possible for the LPI
interrupt to be lost around the specified LPI.
0x47,
SYN_PT_TABLE_WRITE_FAIL_BYTE
An attempt was made to write-back a
subblock of interrupts from a Pending
table, with an error received with the
write response.
0x12 Target, bits[29:16]
ID, bits[15:0]
The GIC tries to continue, however, this error
indicates issues with the memory system, and
operation might be unpredictable
4.15.6.2 SPI RAM error records 1-2
SPI RAM error record 1 records RAM ECC errors that are correctable. SPI RAM error record 2
records RAM ECC errors that are uncorrectable.
SPI RAM error records 1-2 are present if SPI RAM ECC is configured.
The GIC-600AE has two SPI RAM, SPI0 and SPI1 that contain the programming for SPIs. SPI0
contains SPIs that have even-numbered IDs, and SPI1 contains SPIs that have odd-numbered IDs.
If a correctable error is detected in SPI RAM, it is corrected and the error is reported in error record
1. See 4.15.5 Error recovery and fault handling interrupts on page 70 for information about the
error counters and interrupt generation options.
Correctable errors do not require software to take any action within the GIC. However, software
can choose to track error locations in case a RAM row or column can be repaired, and the RAM has
repair capability.
The GICT_ERR1MISC0 reports data for SPI error records 1-2 shown in the following table.
Table 4-9: SPI RAM errors, records 1-2
Record GICT_ERR1MISC0.Data
1 = Correctable Bit location, ID, bits[log
2
(SPIs)+]
2 = Uncorrectable ID, bits[log
2
(SPIs) − 1:0]
The RAM address can be determined from the ID >> 1. ID[0] specifies the SPI RAM number.
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