Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
If an SPI has an uncorrectable error, GICD_ICERRRn identifies the SPI. While in this error state,
the interrupt reverts to a disabled, Secure Group 0, edge-triggered SPI, and Non-secure access is
controlled by GICD_FCTLR.NSACR. This enables Secure software to control whether Non-secure
accesses can set the interrupt to pending while in the errored state.
For uncorrectable errors, software is required to perform the following recovery sequence:
1.
Read the error record, to determine if an uncorrectable error has occurred.
2.
Clear the error record, to enable future errors to be tracked.
3.
Read all GICD_ICERRRn registers, so that you can identify the SPIs that have errors. The
GICD_ICERRRn registers must be read from the Secure side.
If the error record reports only one error, the block that contains the error can be determined
using the ID in the GICT_ERR2MISC0 register, by calculating the block number as 1 + (ID / 32).
However, if an overflow occurs, all GICD_ICERRRn registers must be checked.
4.
If necessary, read out any of the current programmed states. This includes programmed
data that is corrupted and generates an error, unless GICT_ERR0CTRL.UE is disabled. We
recommend that intended programming is stored in memory so that this step is not required.
5.
Write to GICD_ICENABLERn, to disable all interrupts that have errors.
6.
Write 1 to the GICD_ICERRRn bits that step 3 on page 77 indicates are showing an SPI
error. This write clears the interrupt error and reverts the corresponding GICD_IGROUPRn,
GICD_IGRPMODRn, GICD_ICFGRn, and GICD_NSACRn bits to their default values.
7.
Read GICD_ICERRRn, to check that the error has cleared. If the error remains, then clear all
the GICD_CTLR group enables so that it forces all SPIs to return to their owner chips. When
GICD_CTLR.RWP returns to 0, repeat the write to GICD_ICERRRn. When the error clear is
accepted, you can re-enable the group enables.
8.
Reprogram the interrupt to the intended settings.
9.
If the interrupt is reprogrammed to be level-sensitive, write to GICD_ICPENDRn to ensure that
any edge-sensitive pending bits are cleared.
10.
If the interrupt is edge-triggered, we recommend that software checks the device, if possible, in
case an edge is lost.
11.
Ensure that the active bit is set correctly depending on whether it is being processed. Clear
the active bit using GICD_ICACTIVE to ensure that the interrupt is delivered when it is set to
pending in the future. However, if the interrupt is being processed in a core, the interrupt might
be delivered again before it is deactivated.
12.
Re-enable the reprogrammed interrupts by writing to GICD_ISENABLER.
13.
Recheck the error record, to ensure that no more errors are reported. If necessary, repeat step
2 on page 77.
4.15.6.3 SGI RAM error records 3-4
SGI RAM error record 3 records RAM ECC errors that are correctable. SGI RAM error record 4
records RAM ECC errors that are uncorrectable.
SGI RAM error records 3-4 are present if SGI RAM ECC is configured.
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