ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
Table 3-3: Distributor ACE-Lite subordinate interface acceptance capabilities
Attribute Capability
Combined acceptance capability 3
Read acceptance capability 2
Read data reorder depth 1
Write acceptance capability 2
The GIC-600AE uses awatop_s, a<x>cache_s, a<x>domain_s, a<x>snoop_s, and a<x>bar_s
signals to detect cache maintenance operations and barrier transactions that are responded to
in a protocol-compliant manner but are otherwise ignored. The GIC-600AE also ignores other
Cacheability, Shareability, and protection settings, except for the a<x>prot_s[1] security signal.
If you are connecting to an AXI3 or AXI4 port, then awatop_s, a<x>domain>_s, a<x>snoop_s,
a<x>bar_s and, for AXI3, a<x>len[7:4] signals must all be tied LOW.
The GIC-600AE has a separate awakeup_s signal to force the GIC to wakeup when it is
hierarchically clock gated through the Q-Channel. The awakeup_s signal must be connected to a
cleanly registered version of (awvalid_s | arvalid_s signal) to ensure that the GIC does not request to
be woken up due to incoming signal glitches.
The GIC-600AE address map has multiple pages. The number of pages and the address aliasing
depends on your configuration. See 5.1 Register map pages on page 95.
You must set up the system address map so that each core accesses the GICD page on its local
chip at the same address. All other pages must be globally accessible, although access of pages on
a remote chip by a core is expected to be rare.
Related information
Register map pages on page 95
3.1.3 Distributor ACE-Lite manager interface
The GICD uses the AMBA
®
ACE-Lite manager interface to access all pending, property, and
translation tables that are allocated to the GIC. If LPIs are not supported, then this interface is not
present.
The interface can be configured to be 64-bit, 128-bit, or 256-bit wide.
The following table shows the issuing capabilities of the Distributor ACE-Lite manager interface.
Table 3-4: Distributor ACE-Lite manager interface issuing capabilities
CapabilityAttribute
Read Write Combined
256-bit aligned read and writes to any Pending table 3 3 3
8-bit read and writes to any Pending table 1 1 1
256-bit aligned reads to the Property table 1 0 1
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