ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[2]
11
EnableGrp1Secure In systems that enable two Security states, when GICD_CTLR.DS == 0, then:
•
For Secure reads, returns the Group 1 Secure CPU interface enable.
•
For Non-secure reads, returns zero.
In systems that only enable a single Security state, when GICD_CTLR.DS == 1, then this bit returns zero.
[1]
11
EnableGrp1NSecure In systems that enable two Security states, when GICD_CTLR.DS == 0, then:
•
For Secure reads, this bit returns the Group 1 Non-secure CPU interface enable.
•
For Non-secure reads, when GICD_CTLR.ARE_NS == 1, this bit returns the Group 1 Non-secure CPU
interface enable.
•
For Non-secure reads when GICD_CTLR.ARE_NS == 0, this bit returns zero.
In systems that only enable a single Security state, when GICD_CTLR.DS == 1, this bit returns the Group 1
CPU interface enable.
[0]
11
EnableGrp0 In systems that enable two Security states, when GICD_CTLR.DS == 0, then:
•
For Secure reads, this bit returns the Group 0 CPU interface enable.
•
For Non-secure reads when GICD_CTLR.ARE_NS == 0, this bit returns the Group 1 Non-secure CPU
interface enable.
•
For Non-secure reads when GICD_CTLR.ARE_NS == 1, this bit returns zero.
In systems that only enable a single Security state, when GICD_CTLR.DS == 1, this bit returns the Group 0
CPU interface enable.
5.5.2 GICR_IERRVR, Interrupt Error Valid Register
This register indicates if the SGI or PPI data has been corrupted in SRAM. You can use this register
to clear an error.
Configurations
This register is available in all configurations.
Attributes
Width
32-bit
Functional group
See 5.5 Redistributor registers for SGIs and PPIs summary on page 130 for the address
offset, type, and reset value of this register.
Usage constraints
Only accessible by Secure accesses.
11
These bits are a copy of the CPU interface group enables for the core corresponding to this Redistributor. These
copies are undefined when ProcessorSleep or ChildrenSleep is set for a core, because the core is presumed to
be powered down. Upstream write packets maintain these copies that can de-synchronize after an incorrect
powerdown sequence. This register enables you to debug this scenario. For more information, see the Arm
®
Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 133 of 268