Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
4.16.7 LPI multichip operation
The GIC-600AE does not use physical target addresses, so GITS_TYPER.PTA == 0. Therefore,
GIC-600AE uses the value of GICR_TYPER.ProcessorNumber to route all LPIs and commands to
their targets.
The GIC-600AE splits the GITS_TYPER.ProcessorNumber value into two fields, Chip_ID and the
padded linear on-chip core number.
The width of the padded on-chip core number field is defined by the max_pe_on_chip configuration
parameter. This parameter sets the maximum number of cores or threads on a single chip in
the configuration. The width of the linear on-chip core number field is discoverable through
GICD_CFGID.PEW.
For example, if max_pe_on_chip = 17, the width of the lower part of the on-chip core number field
is ceil[log
2
(17)] = 5 bits. Therefore, the ProcessorNumber value of the first core on chip 1 is 0x20,
the value of the second core on chip 1 is 0x21, the value of the first core on chip 2 is 0x40.
The following figure shows the ProcessorNumber fields with typical values.
Figure 4-4: ProcessorNumber fields
16124 12488
000001000
Chip_ID Core number
100001000
Chip 1, Core 1 = 0x20
Chip 1, Core 2 = 0x21
000000100
Chip 2, Core 1 = 0x40
If software attempts to access a chip that does not exist, is offline, or access a core that does not
exist, the request is dropped and reported through the ITS command and translation error records.
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