Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
6.2.7 Lock and key mechanism
The FMU registers are protected against inadvertent writes by a lock and key mechanism.
The FMU registers are in a locked state after reset. If the register file is locked, then any write
access to any register other than the FMU_KEY register is ignored.
The register file is unlocked when a write to FMU_KEY occurs that satisfies all of the following
conditions:
•
is Secure
•
is for 32 bits. That is, all write strobes.
•
the bottom 8 bits are 0xBE
The register file is locked again when a write occurs that satisfies all of the following conditions:
•
is a Secure write
•
is any width and any write strobes
•
is to any register except for FMU_KEY
A write to FMU_KEY, when unlocked, leaves the register file unlocked only if the write satisfies the
criteria for unlocking the register file. Otherwise, it locks the register file.
If the register file is unlocked, then FMU_KEY reads as 0x00000BE. Otherwise, FMU_KEY reads as
0x00000000.
Non-secure accesses never succeed and never affect the locked state of the register file.
Accessing 64-bit FMU registers
Some of the FMU registers are 64-bit registers, but the APB interface width is 32 bits. When in
unlocked state, the FMU allows for two consecutive writes to update the same 64-bit register
without requiring unlocking again before the second write. In this sequence, both the writes are
Secure, with all write strobes to the same register, except that the second write targets the other
half of that register.
For example, the following sequence is successful in updating the register contents:
1.
Secure write of 0xBE to FMU_KEY, with all write strobes asserted.
2.
32-bit Secure write to FMU_ERR0CTLR[63:32] addr 0x0C, all write strobes asserted.
3.
32-bit Secure write to FMU_ERR0CTLR[31:0] addr 0x08, all write strobes asserted.
This behavior is permitted to allow for the case when the APB interconnect splits a single 64-bit
register access and presents it to the FMU in any order.
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