Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Implementation-defined features
Appendix B Implementation-defined
features
The GIC-600AE implements features that are defined in the GICv3 architecture. Many of these
features also have options in the GICv3 architecture, which determine behavior that is specific to
the GIC-600AE. These features and options are configurable at build time.
The following table summarizes the implementation-defined features of the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4 that the
GIC-600AE uses. The table also gives references to sections within this document that provide
information about implementation-defined behavior of the GIC-600AE.
Table B-1: Declared implementation-defined features
Architectural specification
reference
GICv3
architecture
feature
Chapter Section
Description
1 of N model Introduction Models for
handling
interrupts
See 4.5 SPI routing and 1 of N selection on page 54
Direct LPI
support
GIC
partitioning
The GIC logical
components
Direct LPI support is by configuration, if there are no ITS blocks in the system.
ITS to
Redistributor
communications
Locality-
specific
peripheral
interrupts and
the ITS
LPIs This communication occurs over a fully credited AXI4-Stream.
INTIDs Distribution
and routing of
interrupts
INTIDs 16-bit width when supporting LPIs, otherwise the width is set to support the number
of SPIs and SGIs.
All error cases - Pseudocode
throughout the
document
All errors are reported through error records, see 4.15 Reliability, Accessibility, and
Serviceability on page 68.
Message-based
SPIs
Physical
interrupt
handling and
prioritization
Shared
peripheral
interrupts
Pending bits for level sensitive SPIs that are set by writes to GICD_SETSPI_* or
GICA_SETSPI_*, are not affected by writes to GICD_ICPENDRn.
Writes to GICD_CLRSPI_* or GICA_CLRSPI_* have no effect on pending bits set by
GICD_ISPENDRn.
Interrupt
grouping
Physical
interrupt
handling and
prioritization
Interrupt
grouping
All implemented SPIs, SGIs, and PPIs have programmable groups.
Interrupt
enables
Physical
interrupt
handling and
prioritization
Enabling
individual
interrupts
All SGIs have a programmable enable.
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