ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Implementation-defined features
Architectural specification
reference
GICv3
architecture
feature
Chapter Section
Description
Interaction
of group and
individual
interrupt
enables
Interrupts that are disabled through the GICC_CTLR register or the ICC_CTLR_*
registers, are not considered in the selection of the highest pending interrupt and do
not block fully enabled interrupts of a lower priority.
Interrupt
prioritization
Physical
interrupt
handling and
prioritization
Interrupt
prioritization
GIC-600AE supports 32 priority levels, 16 for LPIs that are always Non-secure.
Effects of
disabling
interrupts
Physical
interrupt
handling and
prioritization
Effect of
disabling
interrupts
Interrupts are set pending irrespective of the GICD_CTLR.EnableGrp* settings.
Changing
priority
Physical
interrupt
handling and
prioritization
Interrupt
prioritization.
Changing the
priority of
enabled PPIs,
SGIs, and SPIs.
Reprogramming an IPRIORITYRn register does not change the priority of an active
interrupt. Reprogramming an IPRIORITYRn causes a pending and not active interrupt
to be recalled from the CPU interface so that the new value can be applied.
Direct LPI
registers
Locality-
specific
peripheral
interrupts and
the ITS
LPIs The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and
GICR_SYNCR are supported in configurations that support LPIs but have no ITS
anywhere in the system.
If there is an ITS, these registers, and their locations, are RAZ/WI.
LPI caching Locality-
specific
peripheral
interrupts and
the ITS
LPIs See 4.10 LPI caching on page 63 and 4.9 ITS on page 60.
LPI
Configuration
tables
Locality-
specific
peripheral
interrupts and
the ITS
LPI
Configuration
tables
The GIC-600AE has one GICR_PROPBASER register for all cores on a chip and
therefore points at a single table. Each chip in a multichip configuration can point
to a copy of the table in local memory. See GICR_TYPER.CommonLPIAff for more
information.
When interrupts are sent between chips, they keep the properties associated
with them until the next invalidate. All property fetches are always from the offset
specified in the GICR_PROPBASER of the issuing chip.
LPI Pending
tables
Locality-
specific
peripheral
interrupts and
the ITS
LPI Pending
tables
See the Arm
®
Generic Interrupt Controller Architecture Specification, GIC
architecture version 3 and version 4
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