ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
4.15.6.1 Software error record 0
Software error record 0 records software errors that are uncorrectable.
Record 0 contains software programming errors from a wide range of sources within the
GIC-600AE. In general, these errors are contained. For uncorrected errors, the information that is
provided gives enough information to enable recovery without significant loss of functionality.
We recommend that record 0 is connected to a high priority interrupt. This connection prevents
the record from overflowing if it receives more errors than it is able to process with the possible
loss of information that is required for recovery. See 4.15.5 Error recovery and fault handling
interrupts on page 70 for more information.
The following table describes the syndromes that are recorded in record 0, the reported
information, and recovery instructions.
Table 4-8: Software errors, record 0
GICT_ERR<n>STATUS.IERR
(Syndrome)
GICT_ERR<n>STATUS
.SERR
GICT_ERR<n>MISC0.
Data description
(other bits RES0)
Always packed from
0 (lowest = 0)
Recovery, prevention
0x0, SYN_ACE_BAD
Illegal ACE-Lite subordinate access.
0xE AccessRnW, bit[12]
AccessSparse, bit[11]
AccessSize, bits[10:8]
AccessLength,
bits[7:0]
Repeat illegal access, with appropriate size and
properties.
Full access address is given in GICT_ERR0ADDR.
0x1, SYN_PPI_PWRDWN
Attempt to access a powered down
Redistributor.
0xF Redistributor,
bits[24:16]
Core, bits[8:0]
Ensure that the Redistributor is powered up before
accessing. See GICR_PWRR.
Attempt was made by the core reported in MISC0.
0x2, SYN_PPI_PWRCHANGE
Attempt to power down
Redistributor rejected.
0xF Redistributor,
bits[24:16]
Core, bits[8:0]
Ensure that the core accessing the register, or
all cores with the same GICR_PWRR.RDG if
GICR_PWRR.RDAG is set, has completed the
GICR_WAKER.ProcessorSleep handshake
0x3, SYN_GICR_ARE
Attempt to access GICR or GICD
registers in mode that cannot work.
0xF Core, bits[8:0] Repeat the access to the specified core accessing
the correct register space. That is, if ARE_S and
ARE_NS == 1 then PPI and SGI registers must
be accessed through the GICRx instead of GICD
register space.
0x4, SYN_PROPBASE_ACC
Attempt to reprogram PROPBASE
registers to a value that is not
accepted because another value is
already in use.
0xF Core, bits[8:0] GICR_PROPBASER is shared between all cores
on a chip. When any GICR_CTLR.Enable_LPIs bit
is set, the value is locked and cannot be updated
unless a complete GICR_WAKER.Sleep handshake
is complete.
See 4.6.3 Other power management on page
58.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 72 of 268