ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
GICT_ERR<n>STATUS.IERR
(Syndrome)
GICT_ERR<n>STATUS
.SERR
GICT_ERR<n>MISC0.
Data description
(other bits RES0)
Always packed from
0 (lowest = 0)
Recovery, prevention
0x5, SYN_PENDBASE_ACC
Attempt to reprogram PENDBASE
registers to a value that is not
accepted because another value is
already in use.
0xF Core, bits[8:0] When any GICR_CTLR.Enable_LPIs bit is set, the
Shareability, InnerCache, and OuterCache fields
are locked for the whole chip. They can only be
changed by completing the GICR_WAKER.Sleep
handshake.
See 4.6.3 Other power management on page
58. Otherwise, repeat the register access using
the current global values.
0x6, SYN_LPI_CLR
Attempt to reprogram ENABLE_LPI
when not enabled and not asleep.
0xF Core, bits[8:0] We recommend that you do not clear the
Enable_LPIs bit. Instead, interrupts must be
unmapped using an ITS. If you must clear,
then you must flush the LPI cache using the
GICR_WAKER.Sleep handshake.
See 4.6.3 Other power management on page
58.
0x7, SYN_WAKER_CHANGE
Attempt to change GICR_WAKER
abandoned due to handshake rules.
0xF Core, bits[8:0] GICR_WAKER.ProcessorSleep and
GICR_WAKER.ChildrenAsleep form a 4-phase
handshake. The attempt to change state must
be repeated when the previous transition has
completed.
0x8, SYN_SLEEP_FAIL
Attempt to put GIC to sleep failed as
cores are not fully asleep.
0xF Core, bits[8:0] All cores must be asleep, using the
GICR_WAKER.ProcessorSleep handshake, before
you flush the LPI cache using GICR_WAKER.Sleep
0x9, SYN_PGE_ON_QUIESCE
Core put to sleep before its Group
enables were cleared.
0xF Core, bits[8:0] The core must disable its group enables before
it toggles the GICR_WAKER.ProcessorSleep
handshake, otherwise, the GIC clears its record of
the Group enables, causing a mismatch between
the GIC and the core
0xA, SYN_GICD_CTLR
Attempt to update GICD_CTLR
was prevented due to Register Write
Pending (RWP) or Group enable
restrictions.
0xF Data, bits[7:0] Software must wait for GICD_CTLR.RWP to be 0
before repeating the GICD_CTLR write. The data
represents the target value.
0x10, SYN_SGI_NO_TGT
SGI sent with no valid destinations.
0xE Core, bits[8:0] If the SGI is required, software must repeat the SGI
from the reported core with a valid target list.
If this level of RAS functionality is required, the
software must track generated SGIs externally.
0x11, SYN_SGI_CORRUPTED
SGI corrupted without effect.
0x6 Core, bits[8:0] An SGI is corrupted due to a RAM error in the
PPI RAM. The RAM error details are reported
separately in record 8. The GIC ignores the SGI
generated from the recorded core. If you want
software to recover from this error, it must use an
external record of the generated SGI.
0x12, SYN_GICR_CORRUPTED
Data was read from GICR register
space that has encountered an
uncorrectable error.
0x6 GICT_ERR0ADDR is
populated
Software has tried to read corrupted data that is
stored in SGI RAM or PPI RAM. Check records 4
and 8, and perform a recovery sequence for those
interrupts.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 73 of 268