ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
GICT_ERR<n>STATUS.IERR
(Syndrome)
GICT_ERR<n>STATUS
.SERR
GICT_ERR<n>MISC0.
Data description
(other bits RES0)
Always packed from
0 (lowest = 0)
Recovery, prevention
0x13, SYN_GICD_CORRUPTED
Data was read from GICD register
space that encountered an
uncorrectable error.
0x6 GICT_ERR0ADDR is
populated
Software has tried to read corrupted data that is
stored in SPI RAM.
Check record 2 and perform a recovery sequence
for those interrupts.
0x14, SYN_ITS_OFF
Data was read from an ITS that is
powered down.
0xF GICT_ERR0ADDR is
populated
Ensure that the qreqn_its<x> signal power control
Q-Channel is in the RUN state before accessing
the relevant ITS
0x18, SYN_SPI_BLOCK
Attempt to access an SPI block that is
not implemented.
0xE Block, bits[4:0] No recovery is required.
Correct the software.
0x19, SYN_SPI_OOR
Attempt to access a non-
implemented SPI using (SET|CLR)SPI.
0xE ID, bits[9:0] Reprogram the issuing device so that it sends a
supported SPI ID
0x1A, SYN_SPI_NO_DEST_TGT
An SPI has no legal target
destinations.
0xF ID, bits[9:0] Before enabling the specified SPI, reprogram the
SPI to target an existing core.
The same SPI might repeat this error several times
and cause an overflow.
0x1B, SYN_SPI_NO_DEST_1OFN
A 1 of N SPI cannot be delivered due
to bad GICR_CTRL.DPG<0|1NS|1S>
or GICR_CLASSR programming.
0xF ID, bits[9:0] Ensure that there is at least one valid target for
the specified 1 of N interrupt, that is, ensure that
at least one core has acceptable DPG and CLASS
settings to enable delivery.
The same SPI might repeat this error several times
and cause an overflow.
0x1C, SYN_COL_OOR
A collator message is received for
a non-implemented SPI, or is larger
than the number of owned SPIs in a
multichip configuration.
0xF ID, bits[9:0] In a multichip configuration, ensure that there are
enough owned SPIs to support all SPI wires that
are used. Any unsupported interrupts must be
disabled at the source.
0x1D, SYN_DEACT_IN
A Deactivate command to a
nonexistent SPI, or with incorrect
groups set. Deactivate commands
to LPI and nonexistent PPI are not
reported.
0xE None A Deactivate command occurred to a
nonexistent SPI, or that SPI group prevents the
deactivate occurring. Software must check the
active states of SPIs.
0x1E, SYN_SPI_CHIP_OFFLINE
An attempt was made to send an SPI
to an offline chip.
0xF ID, bits[9:0] Software must disable or retarget interrupts that
are targeted at offline cores
0x28, SYN_ITS_REG_SET_OOR
An attempt was made to set an Out-
of-Range (OOR) interrupt. Only valid
when GICR LPI injection registers are
supported.
0xE Core, bits[24:16]
Data, bits[15:0]
Software must reprogram the source device to
only create legal LPI IDs
0x29, SYN_ITS_REG_CLR _OOR
An attempt was made to clear an
OOR interrupt. Only valid when
GICR LPI injection registers are
supported.
0xE Core, bits[24:16]
Data, bits[15:0]
Software must not attempt to clear nonexistent
LPIs
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