Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-47: GICP_EVTYPERn bit assignments
31 30 0
EVENT
781516
EVENT_TYPEOVFCAP
1718
ReservedReserved
Table 5-59: GICP_EVTYPERn bit descriptions
Bits Name Description
[31] OVFCAP When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set
[30:18] - Reserved
[17:16] EVENT_TYPE Event tracking type:
0b00 Count events
0b10 MaximumEvent
0b01, 0b11 Reserved
[15:8] - Reserved
[7:0] EVENT Event identifier. See Table 5-60: GICP_EVTYPERn.EVENT field encoding on page 165.
All events reset to an unknown value. Registers corresponding to unimplemented counters are
RES0.
The following table shows the events that the GIC can count.
Table 5-60: GICP_EVTYPERn.EVENT field encoding
EventID Event Description Filter
0x0 CLK Clock cycle None
0x1 CLK_NG Clock cycle that prevents Q-Channel clock gating None
0x2-0x3 - Reserved -
0x4 DN_MSG Downstream message to core excluding PPIs Target
0x5 DN_SET Set to core SPIs and LPIs Target/ID
range
0x6 DN_SET1OFN Set to core, which is a 1 of N interrupt Target/ID
range
0x7 - Reserved -
0x8 UP_MSG Upstream message from core Target
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