ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
EventID Event Description Filter
0x9 UP_ACT Upstream activate Target/ID
range
0xA UP_REL Upstream release Target/ID
range
0xB UP_ACTREL Upstream activate or release. Target/ID
range
0xC UP_SET_COMP A set followed by an activate. This event counts the set and then decrements on
release.
Target/ID
range
0xD UP_DEACT Upstream deactivate. SPIs only. Target/ID
range
0x10 SGI_BRD Broadcast SGI messages. Target = source. Target/ID
range
0x11 SGI_TAR Targeted SGI messages. Target = source. Target/ID
range
0x12 SGI_ALL All SGI messages. Target = source. Target/ID
range
0x13 SGI_ACC Accepted SGI. Target = source. Target/ID
range
0x14 SGI_BRD_CC_IN Broadcast SGI message from cross-chip ID range/Chip
0x15 SGI_TAR_CC_IN Targeted SGI message from cross-chip ID range/Chip
0x16 SGI_TAR_CC_OUT Targeted SGI sent cross-chip Chip/ID range
0x20 ITS_NLL_LPI Incoming LPI Target/ID
range/ITS
0x21 ITS_LL_LPI Incoming low latency LPI Target/ID
range/ITS
0x22 ITS_LPI Incoming LPI (or low latency) Target/ID
range/ITS
0x23 ITS_LPI_CMD Incoming LPI command Target/ID
range/ITS
0x24 ITS_DID_MISS Number of DeviceID cache misses Target/ID
range/ITS
0x25 ITS_VID_MISS Number of EventID cache misses Target/ID
range/ITS
0x26 ITS_COL_MISS Number of Collection cache misses Target/ID
range/ITS
0x27 ITS_LAT Latency of the ITS transaction Target/ID
range/ITS
0x28 ITS_MPFA Number of free slots during translation Target/ID
range/ITS
0x29 LPI_CC_OUT LPI sent cross-chip ID range/Chip
0x2A LPI_CMD_CC_OUT LPI command sent cross-chip ID range/Chip
0x2B LPI_CC_IN LPI coming in from cross-chip Target/ID
range/Chip
0x2C LPI_CMD_CC_IN LPI command coming in from cross-chip Target/ID
range/Chip
0x30 LPI_OWN_STORED LPI stored in own location. Prevents clock gating and Q-Channel clock gating. -
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