ARM CoreLink GIC-600AE User Manual

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Offset Name Type Reset Width Description Architecture
defined?
0x0024 GICD_SAC RW
Tie-off dependent
2
32 Secure Access Control register No
0x0028-
0x003C
- - - - Reserved -
0x0040 GICD_SETSPI_NSR WO - 32 Non-secure SPI Set Register Yes
0x0044 - - - - Reserved -
0x0048 GICD_CLRSPI_NSR WO - 32 Non-secure SPI Clear Register Yes
0x004C - - - - Reserved -
0x0050
GICD_SETSPI_SR
3
4
WO - 32 Secure SPI Set Register Yes
0x0054 - - - - Reserved -
0x0058
GICD_CLRSPI_SR
3
4
WO - 32 Secure SPI Clear Register Yes
0x005C-
0x007C
- - - - Reserved -
0x0080-
0x00FC
GICD_IGROUPRn
4
RW 0x0 32 Interrupt Group Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0100-
0x017C
GICD_ISENABLERn RW 0x0 32 Interrupt Set-Enable Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0180-
0x01FC
GICD_ICENABLERn RW 0x0 32 Interrupt Clear-Enable Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0200-
0x027C
GICD_ISPENDRn RW SPI signal
dependent
32 Interrupt Set-Pending Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0280-
0x02FC
GICD_ICPENDRn RW SPI signal
dependent
32 Interrupt Clear-Pending Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0300-
0x037C
GICD_ISACTIVERn RW 0x0 32 Interrupt Set-Active Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0380-
0x03FC
GICD_ICACTIVERn RW 0x0 32 Interrupt Clear-Active Registers, n = 0-31, but n=0 is
Reserved
Yes
0x0400-
0x07FC
GICD_IPRIORITYRn RW Security dependent 32 Interrupt Priority Registers, n = 0-255, but n=0-7 are
Reserved when affinity routing is enabled
Yes
0x0800-
0x0BFC
- - - - Reserved -
0x0C00-
0x0CFC
GICD_ICFGRn RW 0x0 32 Interrupt Configuration Registers, n = 0-63, but n=0-1
are Reserved
Yes
0x0D00-
0x0D7C
GICD_IGRPMODRn RW 0x0 32 Interrupt Group Modifier Registers, n = 0-31, but n=0 is
Reserved. If GICD_CTLR.DS == 1, then this register is
RAZ/WI.
Yes
0x0D80-
0x0DFC
- - - - Reserved -
2
The reset values of GICD_SAC.GICTNS and GICD_SAC.GICPNS are controlled by the gict_allow_ns and
gicp_allow_ns tie-off signals respectively.
3
The existence of this register depends on the configuration of the GIC-600AE. If Security support is not included,
then this register does not exist.
4
This register is only accessible from a Secure access.
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ARM CoreLink GIC-600AE Specifications

General

Brand	ARM
Model	CoreLink GIC-600AE
Category	Controller
Language	English