Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
None
Bit descriptions
Figure 5-40: GICT_ERR<n>MISC0 bit assignments
Data
31
0
Count
63 42 41 40 39
32
REReserved
Overflow
Table 5-50: GICT_ERR<n>MISC0 bit descriptions
Bits Name Description
[63:42] - Reserved, RAZ
[41] RE Rounding error.
The rounding error counter is under-reporting.
[40] Overflow Sticky overflow bit:
0 counter has not overflowed
1 counter has overflowed
If the corrected fault handling interrupt is enabled, then the GIC-600AE generates a fault handling interrupt.
[39:32] Count Error count.
Error counter is not 0 or is more than 13+. Incremented for each corrected error or uncorrectable error that does not
match the recorded syndrome.
[31:0] Data Information that is associated with the error. A description of each error code is given in one of the following tables:
•
Table 4-8: Software errors, record 0 on page 72
•
Table 4-9: SPI RAM errors, records 1-2 on page 76
•
Table 4-10: SGI RAM errors, records 3-4 on page 78
•
Table 4-11: PPI RAM errors, records 7-8 on page 79
•
Table 4-12: LPI RAM errors, records 9-10 on page 80
•
Table 4-13: ITS RAM errors, records 11-12 on page 80
•
4.15.6.7 ITS command and translation error records 13 and beyond on page 81
The following table shows the Data field encoding for each error record and syndrome.
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