Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description Type
[10] - Reserved, RAZ/WI -
[9] QD Q-Channel deny:
0 Do not deny Q-Channel requests
1 Always deny Q-Channel requests
RW
[8] AEE Access error enable:
0 Do not enable reporting of subordinate access errors
1 Enable reporting of subordinate access errors
Writes ignored if the ITS is not quiescent.
RW
[7:4] CGO Clock gate override. One bit per clock gate:
0 Use full clock gating
1 Leave clock running. If clock gates are not implemented, then you must use this value.
The clock gate bit assignments are:
Bit[7], CGO[3] Map fetch
Bit[6], CGO[2] Debug clock
Bit[5], CGO[1] Command clock
Bit[4], CGO[0] CCS, translation logic
RW
[3] CEE Command error enable:
0 Do not enable reporting of command errors and errors from GITS_OPR operations.
1 Enable reporting of command errors and errors from GITS_OPR operations. See 4.15.6.7 ITS command
and translation error records 13 and beyond on page 81.
Writes ignored if the ITS is not quiescent.
RW
[2] UEE Unmapped error enable:
0 Do not enable reporting of unmapped interrupt errors
1 Enable reporting of unmapped interrupt errors
Writes ignored if the ITS is not quiescent.
RW
[1] LTE Latency tracking enable:
0 Disable latency tracking of interrupts
1 Enable latency tracking of interrupts
Writes ignored if the ITS is not quiescent.
RW
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