Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Functional group See 5.6 ITS control register summary on page 136 for the address offset,
type, and reset value of this register.
Usage constraints
If the ITS is not quiescent, then the GIC ignores writes to some fields. The ITS is quiescent when
GITS_CTLR.Quiescent == 1.
Bit descriptions
Figure 5-31: GITS_FCTLR bit assignments
31 3 2 1 0
CGO
7830 29
Reserved
19 18 17 16 15 9
Reserved
IDC
ICC AEE
CEE
UEE
LTE
SIP
IEC
PWE
DCC
10
QD
DMA
11
Reserved
12 4
Table 5-39: GITS_FCTLR bit descriptions
Bits Name Description Type
[31] DCC Disable cache conversion:
0 Use SMMU attribute for AMBA mapping
1 Use Direct attribute for AMBA mapping
Writes ignored if the ITS is not quiescent.
RW
[30] PWE Powerdown when enabled:
0 Requests GITS_CTLR.Quiescent to indicate that the ITS is quiescent and can be powered down.
1 Do not request GITS_CTLR.Quiescent to indicate that the ITS is quiescent.
RW
[29:19] - Reserved, RAZ/WI -
[18] IEC Invalidate Event cache:
0 No effect
1 Invalidate Event cache
WO
[17] IDC Invalidate Device cache:
0 No effect
1 Invalidate Device cache
WO
[16] ICC Invalidate Collection cache:
0 No effect
1 Invalidate Collection cache
WO
[15:12] - Reserved, RAZ/WI -
[11] DMA Enable translation memory reads through the Distributor to meet PCIe dependency requirements:
0 All memory accesses through ACE-Lite manager interface
1 Enable translation memory reads through Distributor
RW
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