ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
3-12 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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3.2.8 ColumnWidth field, MBIR[3:2]
The ColumnWidth field specifies the number of columns in each block of RAM in the
array under test. The column address is always encoded in the least significant bits of
the RAM address, so the number of columns determines the number of bits used. This
information is important for the correct operation of certain MBIST operations, for
example bit-line stress testing and writing a true physical checkerboard pattern to the
array.
b00000000000000001000 Instruction tag RAM arrays 2and 3
b00000000000000010000 Instruction data RAM way 0 (block 0 and 1)
b00000000000000100000 Instruction data RAM way 1 (block 2 and 3)
b00000000000001000000 Instruction data RAM way 2 (block 4 and 5)
b00000000000010000000 Instruction data RAM way 3 (block 6 and 7)
b00000000000100000000 Global History Buffer
b00000000001000000000 TLB RAM array 0
b00000000010000000000 TLB RAM array 1
b00000000100000000000 Data tag RAM arrays 0 and 1
b00000001000000000000 Data tag RAM arrays 2and 3
b00000010000000000000 Data data RAM way 0 (block 0 and 4)
b00000100000000000000 Data data RAM way 1 (block 1and 5)
b00001000000000000000 Data data RAM way 2 (block 2 and 6)
b00010000000000000000 Data data RAM way 3 (block 3 and 7)
b00100000000000000000 Douter RAM
b01000000000000000000 SCU tag RAM arrays 0 and 1
b10000000000000000000 SCU tag RAM arrays 2 and 3
Table 3-9 ArrayEnables field encoding (continued)
ArrayEnables MBIR[23:4] RAM name

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST