MBIST Instruction Register
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 3-3
Restricted Access Non-Confidential
MaxXAddr Specifies the number of bits in the X-address counter.
MaxYAddr Specifies the number of bits in the Y-address counter.
DataWord Data seed to be used during test. These 4 bits are replicated 16
times to form 64 bits of data.
ArrayEnables Specifies the RAM under test.
ColumnWidth Specifies 4, 8, 16, or 32 columns per block of RAM.
CacheSize Specifies a cache size of 16KB, 32KB, or 64KB.
Field descriptions on page 3-4 describes the MBIR fields in more detail.
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