26
2467S–AVR–07/09
ATmega128
ation is in progress, the write operation will be completed provided that the power supply voltage
is sufficient.
I/O Memory The I/O space definition of the ATmega128 is shown in “Register Summary” on page 362.
All ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O registers within the address range $00
- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value
of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction
set section for more details. When using the I/O specific commands IN and OUT, the I/O
addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and
ST instructions, $20 must be added to these addresses. The ATmega128 is a complex micro-
controller with more peripheral units than can be supported within the 64 location reserved in
Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is
replaced with SRAM locations when the ATmega128 is in the ATmega103 compatibility mode.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O register, writing a one back into any flag read as set,
thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and peripherals control registers are explained in later sections.
External Memory
Interface
With all the features the External Memory Interface provides, it is well suited to operate as an
interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-
display, A/D, and D/A. The main features are:
•
Four different wait-state settings (including no wait-state).
• Independent wait-state setting for different extErnal Memory sectors (configurable sector size).
• The number of bits dedicated to address high byte is selectable.
• Bus-keepers on data lines to minimize current consumption (optional).
Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM
becomes available using the dedicated External Memory pins (see Figure 1 on page 2, Table 27
on page 73, Table 33 on page 77, and Table 45 on page 85). The memory configuration is
shown in Figure 11.
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