68
2467S–AVR–07/09
ATmega128
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to
disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 25 summarizes the control signals for the pin value.
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding latch consti-
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay. Figure 31 shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 31. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
Table 25. Port Pin Configurations
DDxn PORTxn
PUD
(in SFIOR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes
Pxn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
in r17, PINx
0xFF
0x00
t
pd, max
XXXXXX
t
pd, min
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