100
2467S–AVR–07/09
ATmega128
Figure 39. Fast PWM Mode, Timing Diagram
The Timer/Counter overflow flag (
TOV0) is set each time the counter reaches Max If the interrupt
is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Set-
ting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM01:0 to 3 (See Table 54 on page 105). The actual OC0 value
will only be visible on the port pin if the data direction for the port pin is set as output. The PWM
waveform is generated by setting (or clearing) the OC0 Register at the compare match between
OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the coun-
ter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be
a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a
constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0 to toggle its logical level on each compare match (COM01:0 = 1). The waveform
generated will have a maximum frequency of f
oc0
= f
clk_I/O
/2 when OCR0 is set to zero. This fea-
ture is similar to the OC0 toggle in CTC mode, except the double buffer feature of the output
compare unit is enabled in the fast PWM mode.
TCNTn
OCRn Update
and
TOVn Interrupt Flag Set
1
Period
2 3
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Interrupt Flag Set
4 5 6 7
f
OCnPWM
f
clk_I/O
N 256⋅
------------------=
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