iv
2467S–AVR–07/09
ATmega128
Analog to Digital Converter 230
Features 230
Operation 232
Starting a Conversion 232
Prescaling and Conversion Timing 233
Changing Channel or Reference Selection 235
ADC Noise Canceler 236
ADC Conversion Result 241
JTAG Interface and On-chip Debug System 246
Features 246
Overview 246
Test Access Port – TAP 246
TAP Controller 248
Using the Boundary-scan Chain 249
Using the On-chip Debug System 249
On-chip Debug Specific JTAG Instructions 250
On-chip Debug Related Register in I/O Memory 251
Using the JTAG Programming Capabilities 251
Bibliography 251
IEEE 1149.1 (JTAG) Boundary-scan 252
Features 252
System Overview 252
Data Registers 252
Boundary-scan Specific JTAG Instructions 254
Boundary-scan Related Register in I/O Memory 255
Boundary-scan Chain 255
ATmega128 Boundary-scan Order 266
Boundary-scan Description Language Files 272
Boot Loader Support – Read-While-Write Self-Programming 273
Boot Loader Features 273
Application and Boot Loader Flash Sections 273
Read-While-Write and No Read-While-Write Flash Sections 273
Boot Loader Lock Bits 275
Entering the Boot Loader Program 276
Addressing the Flash During Self-Programming 278
Self-Programming the Flash 279
Memory Programming 286
Program and Data Memory Lock Bits 286
Fuse Bits 287
Signature Bytes 289
Calibration Byte 289
Parallel Programming Parameters, Pin Mapping, and Commands 290
Parallel Programming 292
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