Table 16-4: Tera Term serial settings
4. Reset or power-cycle the module.
5. At this point, the procedure varies depending on whether or not an FPGA image is
already present.
If there is an FPGA image present:
a. After the reset, the following output will be shown in the TeraTerm
window:
Figure 16-1: AES-6 FPGA upgrade using Tera Term
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