CPG Compuprint SP 40 - Parallel Interface Loop-Back Connector; Fig. 5.5 Parallel I;F Bi-Directional Loop-Back

Maintenance Manual SP 40
Rev. 005
103
Chapter 5
Test & Diagnostic
5.9.3 Parallel Interface Loop-Back Connector
The schematic diagram is the following:
Fig. 5.5 Parallel I/F bi-directional Loop-back
TP5
1
TP4
1
DATA7
TP3
1
VCC
14
TP6
1
FAULT
TP2
1
R1
10K
U1B
74HC86
4
5
6
ACKAUTO
J1
FINGHER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
7
U2
74HC374
3
4
7
8
13
14
17
18
1
11
2
5
6
9
12
15
16
19
20
10
D0
D1
D2
D3
D4
D5
D6
D7
OC
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VCC
GND
DATA5
TP1
1
DATA0
DATA3
PE
SLCTIN
L2
LEDY
R3
0
VCC
U1D
74HC86
12
13
11
DATA6
R6
1K
BUSYSTR
SLCTINI
R2
10K
DATA2
R4
0
L1
LEDR
U1C
74HC86
9
10
8
C1
1KpF
DATA4
U1A
74HC86
1
2
3
DATA1
VCC
P1
CONN. CENT36
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
20
21
19 1
2
3
4
16
15
14
13
12
11
10
9
8
7
6
5
18
17
R5
1K