To enable PCIe MPS optimization use the ioconfig mps_optimize command. See “ioconfig”
(page 221).
For non-PCIe systems, ioconfig and info io does not display the MPS optimization policy
setting. The Set PCIe MPS Optimization boot manager menu also is not displayed. When you
run the ioconfig mps_optimize [on|off] command from a non-PCIe system, the following
output displays:
-------------
Shell> ioconfig mps_optimize
ioconfig: PCIe MPS optimization is not supported.
Shell> ioconfig mps_optimize on
ioconfig: PCIe MPS optimization is not supported.
Exit status code: Unsupported
Shell>
-----------------
To restore MPS to the default values, use the default clear command. See “default” (page 223).
Processor
The server processor subsystem supports one or two single- or dual-core Itanium processors.
The processor subsystem consists of the following features:
• zx2 chipset, front side bus, memory, and I/O controller (MIOC)
• System clock generation and distribution
• Circuitry for manageability and fault detection
The zx2, MIOC, and the processors are located on the system board. Each processor connects to
the board through a zero insertion force (ZIF) socket.
Memory
The eight server DIMMs attach directly to the system board. The supported DIMMs are
industry-standard, 30 mm (1.18 in) high, PC2-4200 DIMMs. Hot-spare and hot-plug functionality
is not supported.
The server supports the following DIMM sizes:
• 512 MB
• 1 GB
• 2 GB
• 4 GB
The minimum amount of memory supported is 1 GB (two x 512-MB DIMMs). The maximum
amount of memory supported is 32 GB (eight x 4-GB DIMMs).
Figure 1-3 is a block diagram of the server memory that shows data, addresses, and controls that
flow directly to and from the processors. The server has eight memory slots.
Server Subsystems 23
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