Intel Agilex User Manual

The AVST_READY signal sent by the Intel Agilex device to the host is not synchronized with the AVSTx8_CLK or AVST_CLK.
To configure the Intel Agilex device successfully, the host must adhere to the following constraints:
•
The host must drive no more than six data words after the deassertion of the AVST_READY signal including the delay
incurred by the 2-stage register synchronizer.
•
The host must synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer. Here is
Register transfer level (RTL) example code for 2-stage register synchronizer:
always @(posedge avst_clk or negedge reset_n)
begin
if (~reset_n)
begin
fpga_avst_ready_reg1 <= 0;
fpga_avst_ready_reg2 <= 0;
else
fpga_avst_ready_reg1 <= fpga_avst_ready;
fpga_avst_ready_reg2 <= fpga_avst_ready_reg1;
end
end
Where:
—
The AVST_CLK signal comes from either PFL II IP or your Avalon-ST controller logic.
—
fpga_avst_ready is the AVST_READY signal from the Intel Agilex device.
—
fpga_avst_ready_reg2 signal is the AVST_READY signal that is synchronous to AVST_CLK.
You must properly constrain the AVST_CLK and AVST_DATA signals at the host. Perform timing analysis on both signals
between the host and Intel Agilex device to ensure the Avalon-ST configuration timing specifications are met. Refer to the
Avalon-ST Configuration Timing section of the Intel Agilex Device Data Sheet for information about the timing specifications.
Note:
The AVST_CLK signal must run continuously during configuration. The AVST_READY signal cannot assert unless the clock is
running.
Optionally, you can monitor the CONF_DONE signal to indicate the flash has sent all the data to FPGA or to indicate the
configuration process is complete.
If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary
configuration data to the flash memory through the PFL II IP core.
If you use the Avalon-ST Adapter IP core as part of the configuration host, set the Source Ready Latency value between 1-
6.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English