• Auto— For the tool to automatically allocates a block in the flash device to store the data.
• Block—To specify the start and end address of the flash partition.
• Start—To specify the start address of the partition. The tool assigns the end address of the partition based on the
input data size.
e. For Block and Start options, specify the address information.
3.1.10.2.2. Creating Separate PFL II Functions
Follow these steps to create separate PFL II IP instantiations for programming and configuration control:
1. In the IP Catalog locate the Parallel Flash Loader II Intel FPGA IP.
2. On the General tab for What operating mode will be used, select Flash Programming Only.
3. Intel recommends that you turn on the Set flash bus pins to tri-state when not in use.
4. Specify the parameters on the Flash Interface Settings and Flash Programming tabs to match your design.
5.
Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
6. To create a second PFL II instantiation for FPGA configuration, on the General tab, for What operating mode will be
used, select FPGA Configuration.
7. Use this Flash Programming Only instance of the PFL II IP to write data to the flash device.
8.
Whenever you must program the flash memory device, program the CPLD with the flash memory device .pof and update
the flash memory device contents.
9.
Reprogram the host with the production design .pof that includes the configuration controller.
Note: By default, all unused pins are set to ground. When programming the configuration flash memory device through
the host JTAG pins, you must tri-state the FPGA configuration pins common to the host and the configuration flash
memory device. You can use the pfl_flash_access_request and pfl_flash_access_granted signals of the
PFL II block to tri-state the correct FPGA configuration pins.
3.1.10.2.3. Programming CPLDs and Flash Memory Devices Sequentially
This procedure provides a single set of instructions for the Intel Quartus Prime Programmer to configure the CPLD and write
the flash memory device.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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