Intel Agilex - Page 92

Figure 36. Connections for AS Configuration with Multiple Serial Flash Devices
Pin 1
R
UP
R
DN
R
UP
TCK
TDO
TMS
OPEN
TDI
GND
VCCIO_SDM
OPEN
OPEN
GND
G
ND
V
CCIO_SDM
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AS_DATA[3:0]
Config AS x4 Memory
AS_CLK
AS_nCS0[0]
AS_nCS0[1]
AS_nCS0[2]
AS_nCS0[3]
Download cable 10 pin male header (JTAG mode)
DATA[3:0]
DCLK
CS
Configuration
Control Signals
Configuration
Data Signals
Optional
Monitoring
10kΩ
Optional
HPS Data Signals
MSEL
V
CCIO_SDM
3
4
To JTAG Header
or JTAG Chain
TCK
TDO
TDI
TMS
JTAG
Configuration
Pins
FPGA
Image (.rpd)
HPS AS x4 Memory
DATA[3:0]
DCLK
CS
HPS Data
3M Part number : 2510-6002UB
10kΩ
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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Configuration User Guide
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