Intel Agilex - Page 96

Figure 39. AS Programming Using Intel Quartus Prime or Third-Party Programmer
AS_DATA[0]
AS x4 Flash
Intel FPGA
10 kΩ
nSTATUS
nCONFIG
CONF_DONE
OSC_CLK_1
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
AS_DATA[1]
AS_DATA[2]
AS_DATA[3]
AS_CLK
4.7 kΩ
V
CCIO_SDM
GND
V
CCIO_SDM
V
CCIO_SDM
10 kΩ
MSEL [0]/AS_nCSO[0]
MSEL [1]
MSEL [2]
AS fast mode: Pull MSEL [1] low
AS normal mode: Pull MSEL [1] high
AS fast/normal mode: Pull MSEL [2] low
JTAG mode: Pull MSEL [2] high
External clock source
to is optional.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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