Intel Altera MAX 10 FPGA - Page 51

Board
Reference
(J2)
Schematic Signal Name I/O Standard MAX
10/MAX II
Pin Number
Description
77
HSMC_TX_D_P5
2.5 V CMOS inout or
LVDS TX channels-p
AA7 Data bus
78
HSMC_RX_D_P5
(1)
2.5 V CMOS inout or
LVDS RX channels-p
AB7 Data bus
79
HSMC_TX_D_N5
2.5 V CMOS inout or
LVDS TX channels-n
AA6 Data bus
80
HSMC_RX_D_N5
(1)
2.5 V CMOS inout or
LVDS RX channels-n
AB6 Data bus
83
HSMC_TX_D_P6
2.5 V CMOS inout or
LVDS TX channels-p
P10 Data bus
84
HSMC_RX_D_P6
(1)
2.5 V CMOS inout or
LVDS RX channels-p
Y4 Data bus
85
HSMC_TX_D_N6
2.5 V CMOS inout or
LVDS TX channels-n
R10 Data bus
86
HSMC_RX_D_N6
(1)
2.5 V CMOS inout or
LVDS RX channels-n
Y3 Data bus
89
HSMC_TX_D_P7
2.5 V CMOS inout or
LVDS TX channels-p
W10 Data bus
90
HSMC_RX_D_P7
(1)
2.5 V CMOS inout or
LVDS RX channels-p
AB5 Data bus
91
HSMC_TX_D_N7
2.5 V CMOS inout or
LVDS TX channels-n
W9 Data bus
92
HSMC_RX_D_N7
(1)
2.5 V CMOS inout or
LVDS RX channels-n
AA5 Data bus
95
HSMC_CLK_OUT_P1
2.5 V CMOS inout or
LVDS clock out
P13 Clock output 1
96
HSMC_CLK_IN_P1
2.5 V CMOS inout or
LVDS clock in
AA20 Clock input 1
97
HSMC_CLK_OUT_N1
2.5 V CMOS inout or
LVDS clock out
R13 Clock output 1
98
HSMC_CLK_IN_N1
2.5 V CMOS inout or
LVDS clock in
AB21 Clock input 1
101
HSMC_TX_D_P8
2.5 V CMOS inout or
LVDS TX channels-p
W14 Data bus
102
HSMC_RX_D_P8
(1)
2.5 V CMOS inout or
LVDS RX channels-p
W13 Data bus
103
HSMC_TX_D_N8
2.5 V CMOS inout or
LVDS TX channels-n
V13 Data bus
104
HSMC_RX_D_N8
(1)
2.5 V CMOS inout or
LVDS RX channels-n
W12 Data bus
107
HSMC_TX_D_P9
2.5 V CMOS inout or
LVDS TX channels-p
Y14 Data bus
108
HSMC_RX_D_P9
(1)
2.5 V CMOS inout or
LVDS RX channels-p
AB15 Data bus
109
HSMC_TX_D_N9
2.5 V CMOS inout or
LVDS TX channels-n
Y13 Data bus
continued...
A. Development Kit Components
683460 | 2024.11.20
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10 FPGA Development Kit User Guide
51