Thermal/Mechanical Specifications and Design Guide 67
PECI Interface
7.1.2.6.8 DRAM Power Info Read
This read returns the minimum, typical and maximum DRAM power settings and the
maximum time window over which the power can be sustained for the entire DRAM
domain and is inclusive of all the DIMMs within all the memory channels. Any power
values specified by the power limiting entity that is outside of the range specified
through these settings cannot be guaranteed. Since this data is 64 bits wide, PECI
facilitates access to this register by allowing two requests to read the lower 32 bits and
upper 32 bits separately as shown in Table 7- 6. Power and time units for this read are
defined as per the Package Power SKU Unit settings described in Section 7.1.2.7.
7.1.2.6.9 DRAM Power Limit Data Write / Read
This feature allows the PECI host to program the power limit over a specified time or
control window for the entire DRAM domain covering all the DIMMs within all the
memory channels. Actual values are chosen based on DRAM power consumption
characteristics. The units for the DRAM Power Limit and Control Time Window are
determined as per the Package Power SKU Unit settings described in Section 7.1.2.7.
The DRAM Power Limit Enable bit in Figure 7-17 should be set to activate this feature.
7.1.2.6.10 DRAM Power Limit Performance Status Read
This service allows the PECI host to assess the performance impact of the currently
active DRAM power limiting modes. The read return data contains the sum of all the
time durations for which each of the DIMMs has been operating in a low power state.
This information is tracked by a 32-bit counter that wraps around. The unit for time is
determined as per the Package Power SKU Unit settings described in Section 7.1.2.7.
Figure 7-16. DRAM Power Info Read Data
DRAM_POWER_INFO (lower bits)
Reserved
14
Minimum DRAM Power
16
TDP DRAM Power
(Typical Value)
30 015
Reserved
31
DRAM_POWER_INFO (upper bits)
Maximum DRAM Power
3246
Reserved
47
Maximum Time
Window
4854
Reserved
5563
Figure 7-17. DRAM Power Limit Data
DRAM_POWER_LIMIT Data
DRAM
Power Limit
Enable
1523
DRAM Power Limit
14 0
RESERVED
16
Control Time
Window
1731
RESERVED
24