PECI Interface
80 Thermal/Mechanical Specifications and Design Guide
The 2-byte MSR Address field and read data field defined in Figure 7-38 are sent in
standard PECI ordering with LSB first and MSB last.
Figure 7-37. Processor ID Construction Example
Figure 7-38. RdIAMSR()
<Process Name>
13
Byte
Definition
Byte #
02
15
17
Data (1, 2, 4 or 8 bytes) MSB
14
16
18
FCS
Read Length
{0x02, 0x03, 0x05, 0x09)
Cmd Code
0xb1
LSB Data (1, 2, 4 or 8 bytes)
Write Length
0x05
9
11
8
6
Completion
Code
Processor ID
5
13
4
LSB MSR Address MSB
Client Address
10
7
FCS
Host ID[7:1] &
Retry[0]
12
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