SCPI Status Registers 2
Keysight U2722A/U2723A Programmer’s Reference 25
Status Byte Register
The Status Byte summary register reports conditions from the other status
registers. Query data that is waiting in the U2722A/U2723A's output buffer is
immediately reported via message available bit (bit 4). Bits in the summary
register are not latched. Clearing an event register will clear the corresponding
bits in the Status Byte summary register. The message available bit will be cleared
once all the messages in the output buffer, including any pending queries, have
been read.
Bit Definitions: Status Byte Register
The Status Byte summary register will be cleared when:
– you execute the clear status (*CLS) command
– querying the Standard Event register (*ESR? command will clear only bit 4 in
the summary register)
The Status Byte Enable register is cleared when you execute the *SRE 0
command.
Bit number Decimal value Definition
0 Not Used 1 Always zero.
1 Not Used 2 Always zero.
2 Error Queue 4 There is at least one error code in the error queue.
3 Questionable Status Event 8 One or more bits are set in the Questionable Event register (bits must be
enabled in the enable register).
4 Message Available 16 Data is available in the instrument's output buffer.
5 Event Status Byte summary 32 One or more bits are set in the Standard Event register (bits must be
enabled in the enable register).
6 Master Status summary
(Request for Service)
64 One or more bits are set in the Status Byte register (bits must be enabled
in the enable register). Also used to indicate a request for service.
7 Operation Status Event 128 One or more bits are set in the Operation Event register (bits must be
enabled in the enable register).
Please refer to Chapter 13, “IEEE-488.2 Common Commands” on page 111 for
more details of the common IEEE commands mentioned above.
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